2006-2-27

Defect Inspection for Imprint Lithography Using a Die to Database Electron Beam Verification System

• Event: SPIE2006
• L. Jeff Myron, Ecron Thompson, Ian McMackin, Douglas J. Resnick
  Molecular Imprints, Inc., 1807-C West Braker Lane, Austin, TX 78758
  
  Tadashi Kitamura, Toshiaki Hasebe, Shinichi Nakazawa, Toshifumi Tokumoto,NGR Inc., 7F NK Shimurasakaue Bldg., 3-6-7 Azusawa, Itabashi-ku, Tokyo Japan 174-0051
  
  Eric Ainley, Kevin Nordquist, William J. Dauksher Motorola Labs, 2100 East Elliot Road, Tempe, Arizona 85284

ABSTRACT

Imprint lithography has been included on the ITRS Lithography Roadmap at the 32 and 22 nm nodes. Step and Flash Imprint Lithography (S-FIL^™) is a unique method for printing sub-100 nm geometries. Relative to other imprinting processes S-FIL has the advantage that the template is transparent, thereby facilitating conventional overlay techniques. Further, S-FIL provides sub-100 nm feature resolution without the significant expense of multi-element, high quality projection optics or advanced illumination sources. However, since the technology is 1×, it is critical to address the infrastructure associated with the fabrication of templates.

With respect to inspection, although defects as small as 70 nm have been detected using optical techniques, it is clear that it will be necessary to take advantage of the resolution capabilities of electron beam inspection techniques. This paper reports the first systematic study of die-to-database electron beam inspection of patterns that were imprinted using an Imprio 250 system. The die-to-database inspection of the wafers was performed on an NGR2100 inspection system. Ultimately, the most desirable solution is to directly inspect the fused silica template. This paper also reports the results on the first initial experiments of direct inspection fused silica substrates at data rates of 200 MHz.

Three different experiments were performed. In the first study, large (350 -400 nm) Metal 1 and contact features were imprinted and inspected as described above. Using a 12 nm pixel address grid, 24 nm defects were readily detected. The second experiment examined imprinted Metal 1 and Logic patterns with dimensions as small as 70 nm. Using a pixel address of 3 nm, and a defect threshold of 20 nm, a systematic study of the patterned arrays identified problem areas in the design of the pattern layout. Finally, initial inspection of 200 mm fused silica patterned substrates has established proof of concept for direct inspection of imprint templates.

Key words: imprint, lithography, electron beam, inspection, die to database, template