2009-08-31

Tolerance-Based Wafer Verification Methodologies with a Die-to-Database Inspection System

• Japanese Journal of Applied Physics
• Kohji Hashimoto, Satoshi Usui1, Kenji Yoshida1, Satoshi Tanaka, Toshiya Kotani, Shigeki Nojima, Ichirota Nagahama, Osamu Nagano, Yasuo Matsuoka, Yuuichiro Yamazaki, and Soichi Inoue
• Process and Manufacturing Engineering Center, Semiconductor Company, Toshiba Corporation,
  8 Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan
• 1Process and Manufacturing Engineering Center, Semiconductor Company, Toshiba Corporation,
  3500 Matsuoka, Oita 870-0197, Japan

ABSTRACT

With a die-to-database inspection system using electron beam, we have constructed state-of-the-art verification methodologies for the design for manufacturability (DfM), process proximity correction (PPC), minimization of process errors and process fluctuations, and so on. The experimental methodologies make it possible to extract exact hotspots and result in short development turnaround time (TAT) in low k1 lithography. In the methodologies, the die-to-database inspection system, NGR-2100, has remarkable features for the full-chip inspection within reasonable operating time. This system is equipped with tolerance-based “verifiers” and provides higher hotspot extraction accuracy than the conventional optical inspection tool. As a result, hotspots extracted using the system included all killer hotspots extracted by electrical and physical analyses. In addition, the new methodologies are highly advantageous in that they shorten the development TAT by two to four months. In the application to 65-nm-node complimentary metal oxide semiconductor (CMOS) devices, we verified yield improvement using the proposed methodologies.