2024-2-25

Utilization of active contour model with 3D-SEM simulation for see-through BSE image of high voltage SEM

• Event: SPIE Advanced Lithography + Patterning 2024
• Masahiro Oya, Yosuke Okamoto, Shinichi Nakazawa, Kotaro Maruyama, Yuichiro Yamazaki, Shinji Murakami, Yoshihiro Midoh, and Noriyuki Miura
  
  Proc. SPIE 12955, Metrology, Inspection, and Process Control XXXVIII, 129550R, 25 Feb. 2024,
  DOI: 10.1117/12.3011075

ABSTRACT

As semiconductor device structures continue to scale and increase in complexity, direct measurement of overlay and edge placement error (EPE) on actual device patterns has become essential. We propose a high-voltage SEM (HV-SEM) based overlay metrology method using an active contour model combined with electron beam (EB) simulation. Synthetic BSE images representing advanced device structures were generated using EB-simulated image characteristics and used for evaluation. The proposed method demonstrated robust contour extraction under noisy conditions and accurately identified partially obscured lower-layer patterns in see-through BSE images. These results indicate improved measurement accuracy and enhanced applicability of HV-SEM see-through metrology for advanced semiconductor manufacturing.

Key words: High voltage, EBI, SEM, D2DB, CD, EPE, Overlay, CVNet