Apr. 27, 2023
Advanced high voltage e-beam system combined with an enhanced D2DB for on-device overlay measurement
Because high voltage scanning electron microscopy (HV-SEM) based on-device overlay metrology measures the overlay between 3 layers at least, metrology tool-induced error can significantly impact the mask or process correction, which is based on overlay measurement.
Apr. 27, 2023
Simulating HV-SEM imaging of HARand buried features
In this work, important use cases for HV-SEM will be explored by simulation, such as HAR hole / trench imaging with various profiles and depths, buried feature imaging to understand detection and effective resolution with depth for optical overlay cases, and buried defect and void detection, using a new improved electron beam simulator which greatly extends utility of JMONSEL, AMAG SimuSEM, enabling many complex simulation scenarios to be achievable with many improved outputs and other augmentations.
Sep. 15, 2022
Photomask pattern evaluation by massive measurement using Die-to Database
Photomask pattern has been traditionally evaluated with limited gauges with 1D cut-line based measurement method on SEM (Scanning Electron Microscopy) image.
Feb. 22, 2021
Massive e-beam metrology and inspection for analysis of EUV stochastic defect
In the extreme ultraviolet (EUV) lithography process, stochastic defects are randomly generated and can have a significant impact on the yield of high-volume manufacturing (HVM) when printed even at an extremely low probability down to parts per trillion (ppt) level.
Feb. 22, 2021
Improvement of EPE measurement accuracy on ADI wafer, the method of using machine learning trained with CAD
The precise metrology for edge placement error (EPE) is required especially in EUV era. Last year, we proposed new contour extraction algorithm using machine learning and verified the robustness to SEM noise on AEI pattern. In this study,we suggest the method for contour extraction on ADI pattern and improve the EPE measurement accuracy.
Apr. 22, 2020
Massive metrology of 2D logic patterns on BEOL EUVL
At sub10nm nodes of Backend of Line (BEOL) using Extreme Ultraviolet Lithography (EUVL), the requirements of the process window of patterning are extremely tight for parameters such as Critical Dimension (CD) and Overlay which are traditionally managed for the semiconductor process.
Apr. 22, 2020
Realizing more accurate OPC models by utilizing SEM contours
The method to perform Optical Proximity Correction (OPC) model calibration with contour-based input data from both small field of view (SFoV) and large field of view (LFoV) e-beam inspection is presented.
Apr. 22, 2020
Contour extraction algorithm for edge placement error measurement using machine learning
The accurate and precise contour extraction on SEM image is important to measure overlay, improve OPC model, inspect tiny hot-spot, and so on.
Jun. 21, 2019
Edge placement error measurement in lithography process with die to database algorithm
The control of edge placement error (EPE) is playing key role in the patterning of advanced technology node in semiconductor industry.
Jun. 21, 2019
E-beam inspection of single exposure EUV direct print of M2 layer of N10 node test vehicle
Up until now, the main driving force for the semiconductor industry is the continual shrinkage of device feature sizes, thereby incorporating more devices per unit area,
Aug. 16, 2018
Quantitative approach for optimizing e-beam condition of photoresist
Severe process margin in advanced technology node of semiconductor device is controlled by e-beam metrology system and e-beam inspection system with scanning electron microscopy(SEM)image.
Aug. 16, 2018
Overlay of multiframe SEM images including nonlinear field distortions
To reduce charging and shrinkage, CD-SEMs utilize low electron energies and multiframe imaging. This results in every next frame being altered due to stage and beam instability,
Feb. 22, 2016
The new analysis method of PWQ in the DRAM Pattern
In a sub 2Xnm node process, the feedback of pattern weak points is more and more significant. Therefore, it is very important to extract the systemic defect in Double Patterning Technology(DPT),
Feb. 22, 2016
Enhancement of Intrafield Overlay Using a Design based Metrology system
We are going to certify that the overlay values extracted from optical measurement cannot represent the circuit level overlay values and also,
Feb. 22, 2016
Interlayer design verification methodology using contour image
Memory industry has been pursuing endless shrinking technology which increases fabrication complexity. It poses problems between adjacent layers as well as within a single layer.
Feb. 22, 2016
Sub-10 nm lines and spaces patterning using grapho-epitaxial directed self-assembly of lamellar block copolymers
In order to evaluate a directed self-assembly (DSA) technology for semiconductor device manufacturing, we developed a grapho- and chemohybrid coordinated line epitaxy (COOL) process,
Feb. 22, 2016
Prediction of ppm level electrical failure by using physical variation analysis
The quality of patterns printed on wafer may be attributed to factors such as process window control, pattern fidelity, overlay performance, and metrology.
Feb. 22, 2015
Advanced overlay analysis through design based metrology
As design rule shrink, overlay has been critical factor for semiconductor manufacturing. However, the overlay error which is determined by a conventional measurement with an overlay mark based on IBO and DBO often does not represent the physical placement error in the cell area.
Feb. 22, 2015
Directed self-assembly lithography using coordinated line epitaxy (COOL) process
on a 300 mm wafer by applying directed self-assembly (DSA) lithography and pattern transfer for semiconductor device manufacturing. In order to evaluate process performances of DSA,
Feb. 22, 2015
Electrical yield verification of half pitch 15nm patterns using directed self-assembly of PS-b-PMMA
Feb. 23, 2014
Layout optimization of DRAM cells using rigorous simulation model for NTD
DRAM chip space is mainly determined by the size of the memory cell array patterns which consist of periodic memory cell features and edges of the periodic array.
Feb. 23, 2014
Real cell overlay measurement through design based metrology
Until recent device nodes, lithography has been struggling to improve its resolution limit. Even though next generation lithography technology is now facing various difficulties,
Feb. 24, 2013
EUV mask defect analysis from mask to wafer printing
will be installed from this year. EUV mask defect control is the one of the concerns for introducing EUVL to device manufacturing, for current EUV mask defect level is too high to accept for device volume production.
Feb. 24, 2013
In-line E-beam Wafer Metrology and Defect Inspection: The End of an Era for Image-based Critical Dimensional Metrology? New life for Defect Inspection
Metrology measurement and defect inspection steps in routes are more pervasive than many people realize and the number continues to grow. Digging deeper,
Feb. 24, 2013
Application of DBM tool for detection of EUV mask defect
Extreme ultraviolet lithography (EUVL) is one of the most leading lithography technologies for high volume manufacturing.
Feb. 24, 2013
A novel methodology for building robust design rules by using Design Based Metrology (DBM)
This paper addresses a methodology for building robust design rules by using design based metrology (DBM). Conventional method for building design rules has been using a simulation tool and a simple pattern spider mask. At the early stage of the device,
Feb. 12, 2012
Application of DBM system to overlay verification and wiggling quantification for advanced process.
With the shrinkage of semiconductor device scales, advanced semiconductor industries face tremendous challenges in process control.
Feb. 28, 2010
Systematic and Random Defect Control with Design Based Metrology
As technology node of memory devices is approaching around 30nm, the process window is becoming much narrower and production yield is getting more sensitive to tiny defects which used to be not,
Nov. 29, 2009
CD uniformity improvement of sub 60nm contact hole using model based OPC
Generally, rule based optical proximity correction (OPC) together with conventional illumination is used for contact layers, because it is simple to handle and processing times are short.
Aug. 31, 2009
Tolerance-Based Wafer Verification Methodologies with a Die-to-Database Inspection System
With a die-to-database inspection system using electron beam, we have constructed state-of-the-art verification methodologies for the design for manufacturability (DfM),
Apr. 30, 2009
Novel Mask-Qualification Methodology with Die-to-Database Wafer Inspection System
Turn around time (TAT) of mask qualification is one of the most important factors for high-end mask installation to LSI production lines.
Feb. 28, 2009
Hotspot Management for Spacer Patterning Technology with Die-to-Database Wafer Inspection System
We have constructed a hotspot management flow with die-to-database (D2DB) inspection systems of device patterns fabricated by spacer patterning technology,
Feb. 27, 2009
Systematic Defect Filtering and Data Analysis Methodology for Design Based Metrology
Recently several Design Based Metrologies (DBMs) are introduced and being in use for wafer verification. The major applications of DBM are OPC accuracy improvement,
Nov. 30, 2008
The APC (Advanced Process Control) Procedure for Process Window and CDU improvement using DBMs
The downscaling of the feature size and pitches of the semi-conductor device requires enough process window and good CDU of exposure field for improvement of device characteristics and high yield.
Nov. 28, 2008
Novel process proximity correction by the pattern to pattern matching method with DBM
Recently, the dramatic acceleration in dimensional shrink of DRAM memory devices has been observed. For sub 60 nm memory device,
Feb. 28, 2008
Hot Spot Management with Die-to-Database Wafer Inspection System
We constructed hot spot management flow with a die-to-database inspection system that is required for both hot spot extraction accuracy and short development turn-around-time (TAT) in low k1 lithography.
Feb. 27, 2008
Systematic Defect Inspection and Verification for Distributions of Critical Dimension in OPC Models Utilizing Design Based Metrology Tool
As the design technology node becomes smaller, k1 factor is decreasing below 0.3 and optical proximity correction (OPC) divergence is increasing.
Feb. 26, 2008
Wide Applications of Design Based Metrology with Tool Integration
Recently several DBMs(Design Based Metrologies) are introduced for the wafer verification and feed back to DFM. The major applications of DBM are OPC accuracy feed back,
Feb. 25, 2008
A New Robust Process Window Qualification (PWQ) Technique to Perform Systematic Defect Characterization to Enlarge the Lithographic Process Window, using a Die-to-Database Verification Tool (NGR2100)
A new Robust Process Window Qualification (PWQ) Technique to perform systematic defect characterization to enlarge the Lithographic process window is described,
Nov. 30, 2007
Die-to-database verification tool using mass gate measurement and Layout Information for detecting critical dimension errors
With the shrinking of device sizes, the issue of controlling gate critical dimension (CD) is becoming increasingly important.
Sep. 30, 2007
Accuracy of Mask Pattern Contour Extraction with Fine-pixel SEM Images
The specification of photomask patterns is defined for each semiconductor device technology node based on the ITRS (International Technology Roadmap for Semiconductors).
Apr. 30, 2007
A SEM-based System for Photomask Placement Metrology
Mask metrology has long been separated into critical dimension (CD) vs. pattern placement (Registration) in terms of both the parametric definitions as well as measurement techniques applied.
Feb. 28, 2007
Lithography Beyond 32nm: A Role for Imprint?
Feb. 27, 2007
Die-to-Database Verification Tool for detecting CD errors, which are caused by OPC Features, by using Mass Gate Measurement and Layout Information
With the shrinking of device sizes, the issue of controlling gate critical dimension (CD) is becoming increasingly important.
Feb. 26, 2007
Advanced Process Control with Design Based Metrology
K1 factor for development and mass-production of memory devices has been decreased down to below 0.30 in recent years. Process technology has responded with
Feb. 25, 2007
OPC and Design Verification for DFM using Die-to-Database Inspection
The downscaling of the feature size and pitches of the semi-conductor device requires the improvement of device characteristics and high yield continuously.
Feb. 24, 2007
DFM flow by using combination between design based metrology system and model based verification at sub-50nm memory device
As the minimum transistor length is getting smaller, the variation and uniformity of transistor length seriously effect device performance.
Sep. 29, 2006
Direct Die to Database Electron Beam Inspection of Fused Silica Imprint Templates
Imprint lithography has been included on the ITRS Lithography Roadmap at the 32 and 22 nm nodes. Step and Flash Imprint Lithography (S-FILTM) is a unique method for printing sub-100 nm geometries.
Sep. 29, 2006
Introduction of a Die-to-Database Verification Tool for Mask Geometry NGR4000
The NGR4000 enables high precision verification of mask features, by matching Scanning Electron Microscope (SEM) images of the mask features to their intended mask design data.
Jul. 31, 2006
Step and Flash Imprint Lithography for Silicon Integrated Circuit Applications
Small feature imprint lithography has existed for several years. The original technique involved the use of a patterned template which is impressed onto a thermo plastic material,
Jul. 30, 2006
Wafer and mask inspection methods in which layout data and image acquired by scanning electron microscopes are used
NGL2006 Tadashi Kitamura, etc.
Feb. 28, 2006
New OPC Verification Method using Die-to-Database Inspection
We have demonstrated a new OPC verification method using Die-to-Database inspection tool
Feb. 27, 2006
Defect Inspection for Imprint Lithography Using a Die to Database Electron Beam Verification System
Imprint lithography has been included on the ITRS Lithography Roadmap at the 32 and 22 nm nodes. Step and Flash Imprint Lithography
Feb. 26, 2006
A template infrastructure for step-and-flash imprint lithography The templates needed for 1× step-and-flash imprint lithography can be fabricated using extensions of current optical mask manufacturing technology
Over the last 30 years, many different varieties of next generation lithography (NGL) have been proposed as successors to optical lithography,
Dec. 31, 2005
Template Advances in Step and Flash Imprint Lithography
Nano-scale feature replication using imprinting or micro-molding has existed for several years1,2. The Step and Flash邃「 Imprint
Nov. 30, 2005
Introduction of a Die-to-Database Verification Tool for the Entire Printed Geometry of a Die — Geometry Verification System NGR2100
The Geometry Verification System NGR2100 enables verification of the entire die, on a resist or an after-etch wafer, by comparing
May. 31, 2005
Introduction of a Die-to-Database Verification Tool for the Entire Printed Geometry of a Die — Geometry Verification System NGR2100 for DFM
The Geometry Verification System NGR2100 enables verification of the entire die, on a resist or an after-etch wafer, by
Apr. 30, 2005
Introduction of a Die-to-Database Verification Tool for the Entire Printed Geometry of a Die — Geometry Verification System NGR2100 for DFM
The Geometry Verification System NGR2100 enables verification of the entire die, on a resist or an after-etch wafer, by comparing